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 Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY & 67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM Stacked-CSP ( Chip Scale Package)
Description
The M6MGD13TW66CWG-P is a Stacked Chip Scale Package (S-CSP) that contents 128M-bit Flash memory and 64M-bit Mobile RAM in a 72-pin Stacked CSP with leaded solder ball. 128M-bit Flash memory is a 8,388,608 words, single power supply and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR IV (Divided bit-line NOR IV) architecture for the memory cell. All memory blocks are locked and can not be programmed or erased, when F-WP# is Low. Using Software Lock Release function, program or erase operation can be executed.
The M6MGD13TW66CWG-P is suitable for a high performance cellular phone and a mobile PC that are required to be small mounting area, weight and small power dissipation.
Features
Access Time Random Access/ Page Access Flash Mobile RAM Supply Voltage 70ns /25ns (Max.) 85ns /25ns (Max.) FM-VCC=2.7 ~ 3.0V Ta= -40 ~ 85 degree 72pin S-CSP, Ball pitch 0.80mm Outer-ball:Sn-Pb
Ambient Temperature 64M-bit Mobile RAM is a 4,194,304 words high density RAM Package fabricated by CMOS technology for the peripheral circuit and DRAM cell for the memory array. The interface is compatible to an asynchronous SRAM. The cells are automatically refreshed and the refresh control is Application not required for system. The device also has the partial block Mobile communication products refresh scheme and the power down mode by writing the command.
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
1
DU DU NC A5 A4 A0
FCE1#
2
3
4
5
6
7
8
DU DU
A B C D E F G H J K L M
A18 A17 A7 A6 A3 A2 A1
MCE#
MLB# MUB# MOE#
FWP#
GND
FRP#
FWE# FRY/BY#
A16 A8 A10 A9
DQ15
MWE#
A20 A11 A15 A14 A13 A12
GND
NC A19
DQ11
10.8 mm
DU DU
DQ12
A21 NC
DQ13
DU
DQ9
DU
DQ10
GND
FOE#
DQ8
NC NC
FMVCC
DQ6
DQ0
DQ2
DQ4
DQ14
FCE2#
DQ1
DQ3
DQ5
DQ7
DU DU
DU DU
(Top View) 8.5 mm
DU
FM-VCC GND A0-A21 DQ0-DQ15 F-CE1# F-CE2# F-OE# F-WE#
: VCC for Flash / Mobile RAM : GND for Flash / Mobile RAM : Common address for Flash/Mobile RAM : Data I/O : Flash chip enable 1 : Flash chip enable 2 : Output enable for Flash Memory : Write enable for Flash Memory
F-RP# F-WP# F-RY/BY# M-CE# M-OE# M-WE# M-LB# M-UB# NC DU
: Reset power down for Flash : Write protect for Flash : Flash Memory Ready /Busy : Mobile RAM chip enable : Output enable for Mobile RAM : Write enable for Mobile RAM : Lower byte control for Mobile RAM : Upper byte control for Mobile RAM : Non Connection : Don't Use
1
Rev.1.0.48a_bezb
Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY & 67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM Stacked-CSP ( Chip Scale Package)
MCP Block Diagram
FM-Vcc GND
A0 to A21 F-CE1# F-CE2# F-WP# F-RP# F-WE# F-OE#
A0 to A21
128Mbit DINOR IV Flash Memory
F-RY/BY#
DQ0 to DQ15 A0 to A21 M-WE# M-OE# M-UB# M-LB# M-CE# 64Mbit Mobile RAM
Note: In the 128M-bit DINOR(IV) Flash Memory lower 64Mbit is selected by F-CE1#="L" and upper 64Mbit is done by F-CE2#="L". Never select each chip at the same time. In the data sheet there are "VCC"s which mean "FM-VCC" (Common Vcc for Flash / Mobile RAM). In the Flash Memory part they mean OE# and WE# are F-OE# and F-WE#. In the Mobile RAM part UB# , LB#, OE# and WE# are M-UB# , M-LB#, M-OE# and M-WE#, respectively.
Capacitance
Symbol Parameter A21-A0, F-OE#, F-WE#, F-CE1#, F-CE2#, F-WP#, F-RP#, M-OE#, M-WE#, M-CE#, M-LB#, M-UB# DQ15-DQ0, F-RY/BY# Conditions Min. Limits Typ. Max. Unit
CIN
Input capacitance Output Capacitance
Ta=25C, f=1MHz, Vin=Vout=0V
26
pF
COUT
34
pF
2
Rev.1.0.48a_bezb
Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY & 67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM Stacked-CSP ( Chip Scale Package)
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
Keep safety first in your circuit designs!
* Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. * Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). * When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. * Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. * Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
REJ03C0167 (c) 2003 Renesas Technology Corp. New publication, effective April 2003. Specifications subject to change without notice


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